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NB100LVEP91 2.5V / 3.3V Any Level Positive Input to -2.5V / -3.3V / -5V NECL Output Translator
The NB100LVEP91 is a triple any level positive input to NECL output translator. The device accepts LVPECL, LVTTL, LVCMOS, HSTL, CML or LVDS signals, and translates them to differential NECL output signals (-2.5 V / -3.3 V / -5 V). To accomplish the level translation the LVEP91 requires three power rails. The VCC supply should be connected to the positive supply, and the VEE pin should be connected to the negative power supply. The GND pins are connected to the system ground plane. Both VEE and VCC should be bypassed to ground via 0.01 mF capacitors. Under open input conditions, the D input will be biased at VCC/2 and the D input will be pulled to GND. These conditions will force the Q outputs to a low, ensuring stability. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
http://onsemi.com MARKING DIAGRAM*
20 1
20 NB100LVEP91 AWLYYWW
SO-20 DW SUFFIX CASE 751D
1 24 1
24 1
24 PIN QFN MN SUFFIX CASE 485L A WL, L YY, Y WW, W
N100 LP91 ALYW
* Typical Maximum Frequency > 2.0 GHz * 430 ps Typical Propagation Delay * Operating Range: VCC = 2.375 V to 3.8 V; * Q Output will Default LOW with Inputs Open or at GND
VEE = -2.375 V to -5.5 V; GND = 0 V
= Assembly Location = Wafer Lot = Year = Work Week
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device NB100LVEP91DW NB100LVEP91DWR2 NB100LVEP91MN NB100LVEP91MNR2 Package SO-20 SO-20 QFN-24 QFN-24 Shipping 38 Units/Rail 1000/Tape & Reel 93 Units/Rail 3000/Tape & Reel
(c) Semiconductor Components Industries, LLC, 2003
1
January, 2003 - Rev. 2
Publication Order Number: NB100LVEP91/D
NB100LVEP91
Positive Level Input D0 D0 NECL Output Q0 Q0
PIN DESCRIPTION
PIN Dn*, Dn** Qn, Qn VBB VCC VEE GND NC FUNCTION Any Level Inputs ECL Outputs PECL Reference Voltage Output Positive Supply (2.5 V, 3.3 V) Negative Supply (-2.5 V, -3.3 V, -5 V) Ground No Connect
D1 D1
Q1 Q1 VCC VBB GND VEE
D2 D2
Q2 Q2
*Pins will default differentially LOW when left open. **Pins will default to VCC/2 when left open.
GND GND Q1
Q1 GND GND 21 20 19 18 17 16 Q2 Q2 VEE VEE D2 D2
Figure 1. Logic Diagram
Q0 Q0 VCC Q0 20 19 Q0 GND Q1 Q1 GND Q2 18 17 16 15 14 13 Q2 NC 12 11 VCC VCC NB100LVEP91 D0 D0 1 VCC 2 D0 3 4 5 6 7 8 9 D2 10 VEE 1 2 3
24
23
22
NB100LVEP91 4 5 6 7 VBB 8 D1 9 D1 10 11 12 VCC 15 14 13
D0 VBB D1
D1 VBB D2
NC VBB
Warning: All VCC, VEE, and GND pins must be externally connected to Power Supply to guarantee proper operation.
Warning: All VCC, VEE, and GND pins must be externally connected to Power Supply to guarantee proper operation. The thermally conductive exposed pad on package bottom (see case drawing) must be attached to a heat-sinking conduit.
Figure 2. SOIC-20 Lead Pinout (Top View)
Figure 3. QFN-24 Lead Pinout (Top View)
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW 75 kW > 2 kV > 150 V > 2 kV Level 1 UL 94 V-0 @ 0.125 in 446 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34
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NB100LVEP91
MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI VOP Iout IBB TA Tstg qJA qJA qJC Tsol PECL Power Supply NECL Power Supply PECL Input Voltage Operating Voltage Output Current PECL VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) JESD 51-3 (1S-Single Layer Test Board) Thermal Resistance (Junction-to-Ambient) JESD 51- 6 (2S2P Multilayer Test Board) with Filled Thermal Vias Thermal Resistance (Junction-to-Case) Wave Solder 0 lFPM 500 LFPM 0 LFPM std bd <2 to 3 sec @ 248C 20 SOIC 20 SOIC 24 QFN 20 SOIC Parameter Condition 1 GND = 0 V GND = 0 V GND = 0 V GND = 0 V Continuous Surge VI VCC VCC - VEE Condition 2 Rating 3.8 to 0 -5.5 to 0 3.8 to 0 9.3 to 0 50 100 0.5 -40 to +85 -65 to +150 90 60 47.3 30 to 35 265 Unit V V V V mA mA mA C C C/W C/W C/W C/W C
2. Maximum Ratings are those values beyond which device damage may occur.
LVPECL INPUT DC CHARACTERISTICS VCC = 2.5 V, VEE = -2.375 to -5.5 V, GND = 0 V (Note 3)
-40 C Symbol ICC VIH VIL VIHCMR IIH IIL Characteristic Power Supply Current Input HIGH Voltage Input LOW Voltage Input HIGH Voltage Common Mode Range (Differential) (Note 4) Input HIGH Current Input LOW Current D D 0.5 -150 Min 10 1335 GND 0 Typ 14 Max 20 VCC 875 2.5 150 0.5 -150 Min 10 1335 GND 0 25C Typ 14 Max 20 VCC 875 2.5 150 0.5 -150 Min 10 1275 GND 0 85C Typ 14 Max 20 VCC 875 2.5 150 Unit mA mV mV V mA mA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 3. Input parameters vary 1:1 with VCC. VCC can vary +1.3 V / -0.125 V. 4. VIHCMR min varies 1:1 with GND. VIHCMR max varies 1:1 with VCC.
LVPECL INPUT DC CHARACTERISTICS VCC = 3.3 V; VEE = -2.375 V to -5.5 V; GND = 0 V (Note 5)
-40 C Symbol ICC VIH VIL VBB VIHCMR IIH IIL Characteristic VCC Power Supply Current Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Voltage Reference (Note 6) Input HIGH Voltage Common Mode Range (Differential) (Note 6) Input HIGH Current Input LOW Current D D 0.5 -150 Min 10 2135 GND 1775 0 1875 Typ 16 Max 24 VCC 1675 1975 3.3 150 0.5 -150 Min 10 2135 GND 1775 0 1875 25C Typ 16 Max 24 VCC 1675 1975 3.3 150 0.5 -150 Min 10 2135 GND 1775 0 1875 85C Typ 16 Max 24 VCC 1675 1975 3.3 150 Unit mA mV mV mV V mA mA
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 5. Input parameters vary 1:1 with VCC. VCC can vary +0.5 / -0.925 V. 6. VIHCMR min varies 1:1 with GND. VIHCMR max varies 1:1 with VCC.
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NB100LVEP91
NECL OUTPUT DC CHARACTERISTICS VCC = 2.375 V to 3.8 V; VEE = -2.375 V to -5.5 V; GND = 0 V (Note 7)
-40 C Symbol IEE VOH VOL Characteristic VEE Power Supply Current Output HIGH Voltage (Note 8) Output LOW Voltage (Note 8) Min 40 -1 145 -1945 Typ 50 -1020 -1725 Max 60 -895 -1600 Min 38 -1 145 -1945 25C Typ 50 1020 -1725 Max 68 -895 -1600 Min 38 -1030 -1945 85C Typ 50 -1020 -1725 Max 68 -895 -1600 Unit mA mV mV
NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 7. Output parameters vary 1:1 with GND. 8. All loading with 50 W resistor to GND-2 volts.
AC CHARACTERISTICS VCC = 2.375 V to 3.8 V; VEE = -2.375 V to -5.5 V; GND = 0 V
-40 C Symbol Vopp tPLH tPHL0 tSKEW Characteristic Output Voltage Amplitude (Figure 4) Propagation Delay D to Q Pulse Skew (Note 9) Output-to-Output (Note 10) Part-to-Part (Diff) (Note 10) RMS Random Clock Jitter (Note 11) fin = 2.0 GHz Peak-to-Peak Data Dependant Jitter fin = 2.0 Gbps (Note 12) Input Voltage Swing (Note 13) Output Rise/Fall Times Q (20% - 80%) 200 75 fin < 1.0 GHz fin < 1.5 GHz Differential Single-Ended Min 575 525 375 300 Typ 800 750 500 450 15 25 50 0.5 20 800 150 600 650 75 95 125 2.0 Max Min 600 525 375 300 25C Typ 800 750 500 450 15 30 50 0.5 20 200 75 800 150 600 675 75 105 125 2.0 Max Min 550 400 400 300 85C Typ 800 750 550 500 15 30 70 0.5 20 200 75 800 150 650 750 80 105 150 2.0 Max Unit mV ps ps
tJITTER
ps
VPP tr, tf
1200 250
1200 250
1200 275
mV ps
9. Pulse Skew = |tPLH - tPHL| 10. Skews are valid across specified voltage range, part-to-part skew is for a given temperature. 11. RMS Jitter with 50% Duty Cycle Input Clock Signal. 12. Peak-to-Peak Jitter with input NRZ PRBS 231- 1 at 2.0 Gbps. 13. Input voltage swing is a single-ended measurement operating in differential mode. The device has a DC gain of 50.
850 OUTPUT AMPLITUDE (mV) 750 Q AMP 650 550 450 350 RMS JITTER 250 0.5 1.0 1.5 FREQUENCY (GHz) 2.0
10 9.0 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 2.5 RMS JITTER (ps)
Figure 4.
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NB100LVEP91
Application Information
All NB100LVEP91 inputs can accept LVPECL, LVTTL, LVCMOS, HSTL, CML, or LVDS signal levels. The limitations for differential input signal (LVDS, HSTL, LVPECL, or CML) are the minimum input swing of 150 mV
VCC VCC
and the maximum input swing of 3.0 V. Within these conditions, the input voltage can range from VCC to GND. Examples interfaces are illustrated below in a 50 W environment (Z = 50 W)
VCC VCC
Z LVPECL Driver Z 50 W 50 W
D LVPECL91 D LVDS Driver
Z 100 W Z
D LVPECL91 D
GND
VTT = VCC - 2.0 V
GND
VEE
GND
GND
VEE
Figure 5. Standard LVPECL Interface
VCC VCC VCC
Figure 6. Standard LVDS Interface
VCC VCC
50 W Z HSTL Driver Z 50 W 50 W D D LVPECL91 CML Driver Z Z
50 W D LVPECL91 D
GND GND
GND
VEE
GND
GND
VEE
Figure 7. Standard HSTL Interface
VCC VCC
Figure 8. Standard 50 W Load CML Interface
VCC VCC
Z LVTTL Driver 1.5 V (Reference Voltage)
D LVPECL91 D LVCMOS Driver
Z
D LVPECL91
Open
D
GND
GND
VEE
GND
GND
VEE
Figure 9. Standard LVTTTL Interface
Figure 10. Standard LVCMOS Interface (D will default to VCC/2 when left open. A reference voltage of VCC/2 should be applied to D input, if D is interfaced to CMOS signals.)
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NB100LVEP91
Q Driver Device Q 50 W 50 W
D Receiver Device D
V TT V TT = V CC - 2.0 V
Figure 11. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404 AN1405 AN1503 AN1504 AN1560 AN1650 AN1672 AND8002 AND8020 ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques ECLinPS I/O SPICE Modeling Kit Metastability and the ECLinPS Family Low Voltage ECLinPS SPICE Modeling Kit Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Marking and Date Codes Termination of ECL Logic Devices
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NB100LVEP91
PACKAGE DIMENSIONS
SO-20 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-05 ISSUE F
D A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
20X
B 0.25
M
B TA
S
B
S
A
SEATING PLANE
h
18X
e
A1
T
C
QFN 24 MN SUFFIX 24 PIN QFN, 4x4 CASE 485L-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.60 0.80 0.20 REF 0.23 0.28 4.00 BSC 2.70 2.90 4.00 BSC 2.70 2.90 0.50 BSC 0.35 0.45
D
PIN 1 IDENTIFICATION
A B
E
2X DIM A A1 A2 A3 b D D2 E E2 e L
0.15 C
2X
0.15 C A2 0.10 C A
0.08 C
SEATING PLANE
A3 A1 D2
REF
C
L
7 6 12
e
13
E2
24X
b
1 24 19
18
0.10 C A B 0.05 C
e
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NB100LVEP91
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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NB100LVEP91/D

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